When a memory controller receives a memory access request from a processor, and inputs data to or outputs data from a memory such as a DRAM (Dynamic Random Access Memory), the row address and column address are specified, and the memory controller inputs data to or outputs data from the appropriate address. When doing this, it becomes necessary to have a wait time (minimum wait clock necessary for executing an instruction) during each instruction or until the data is actually input or output. This wait time includes a RAS (Row Address Strobe)-to-CAS (Column Address Strobe) delay and CAS latency (CL), and differs depending on the operating speed of the transistor and circuit configuration; also there is a tendency that as the operating frequency becomes higher, the necessary delay increases.
FIG. 10 is a drawing showing the timing for accessing a conventional DRAM memory. The figure shows the timing for 4-bit burst reading of an SDRAM in which tRCD (RAS-to-CAS Delay)=2, CL=2 or 3, and tRP (RAS pre-charge time)=3. An ACT instruction is issued at timing T0, and data is output according to a READ instruction at timing T2 (Q1 to Q4), then pre-charging is performed (PRE instruction) and 9 clocks (tRC) are necessary until ready for the next read instruction (ACT instruction at timing T9). The 5 clocks that do not include the time for actual output of the data cause the effective transfer rate of the memory bus being used to drop because of waiting.
Here, the construction of a memory module will be explained. The number of memory chips that can be mounted in a memory module is set to correspond with the width of the memory bus, and in the case of a 168-pin DIMM (Dual Inline Memory Module) having a 64-bit width, eight memory chips having word configuration×8 bits are grouped to form one rank, and normally the maximum capacity is 16 chips or 2 ranks on both sides. It is possible to switch between these two ranks using a 4-bit chip selection signal, and to specify the rank (memory chips) to be accessed for reading or writing.
When a plurality of ranks or memory modules is connected to a conventional single-channel memory bus, only one rank can be accessed at a time. All of the remaining ranks wait, and a recharge or refresh operation is also performed at the same time, which is inefficient.
As a method for improving the transfer rate, is a method that omits the RAS and CAS specification by burst transfer of a preset length of data stored in successive addresses, or a method that omits the RAS specification and specifies only CAS for successive data in the same RAS. These methods are effective for the input or output of successive data, however, they are not effective when the RAS changes or when performing random access.
Furthermore, as another method for improving the transfer rate is a well-known interleave-access method in which there are two or more memory-bus channels, and increases the transfer rate by alternately performing address mapping (see patent documents 1 and 2). The interleave-access method is also used by recent computer systems.
Also, a multi-bank-access-control device is known (see patent document 3) that controls access of a plurality of memory banks that is accessed from a plurality of processors or a plurality of threads.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-64-64045[Patent Document 2]    Japanese Patent Kokai Publication No. JP-A-3-2943[Patent Document 3]    Japanese Patent Kokai Publication No. JP-P2002-268942A